Semiconductor devices, such as integrated circuits (ICs), are tested physically and/or electrically at numerous intervals during the overall fabrication process. However, the more critical tests of semiconductor devices are conducted during the latter portions of the fabrication and assembly processes. These test processes are commonly referred to as quality assurance (QA) tests and final testing of the devices. For ICs, these QA and final tests typically occur after the wafer fabrication and assembly processes, or when the IC chip is fully assembled or otherwise considered complete. Typically, during a QA or final test process, the static and dynamic electrical performance characteristics of each assembled semiconductor device are tested to ensure that the device meets stringent design requirements and customer specifications. Those devices that pass these final tests are then theoretically ready to be packaged and shipped to the customers.
Semiconductor manufacturers that use existing final test processes typically test the assembled or completed semiconductor devices by lots (about 1,000 devices/lot). Each device in the lot is passed through an automated or semi-automated test system, which contains equipment that measures the device's AC, DC and parametric or dynamic electrical performance characteristics. The test equipment compares each device's performance characteristics with established design criteria and/or customer requirements, and sorts the devices according to the results. Generally, the devices are sorted according to their having "passed" or "failed" the tests. In many instances, final testing also includes physical testing of the assembled devices.
As discussed above, the devices that "pass" these tests are ready to be packaged and shipped to the customers. However, given the high number of devices under test and the possibility that the test equipment may have been defective or improperly calibrated during all or a portion of the test process, a standard practice has been to shelve the "passed" devices temporarily and later retest all or a statistical sample of the "passed" devices. If the results of the retesting process correlate with the results of the original tests, then this correlation allows the assumption that the original tests were completed with no equipment errors or other testing related problems. Consequently, it is then assumed that the original sets of tests must have been correct, and the "passed" devices may then be packaged and shipped. As an alternative to the above-described process of retesting "passed" devices, a random sample is selected from each lot of devices that have been tested. These devices (typically between 5% to 25% of the lot) are then retested. The results of the retests are correlated with the original results, again in order to verify that the test equipment had operated properly during the original tests. This process of retesting samples of lots or just samples of "passed" devices, for tester verification purposes, is commonly referred to (in quality assurance parlance) as the Lot Accept Test process.
A significant problem encountered with the existing Lot Accept Test process is that typically at least four to five lots must be shelved before an acceptable number of "passed" devices are available to provide an adequate base for sampling and retesting. This process of shelving lots wastes a significant amount of time and causes a production logjam that slows down the overall device assembly and final test processes. Unfortunately, the existing final test processes do not increase the quality of the devices, which could have compensated somewhat for the losses in productivity. Moreover, the rehandling of devices during the retest processes can, by itself, cause an increase in the amount of defective devices or at least additional quality assurance risks. One alternative is to purchase additional test systems to increase productivity, but this equipment is very expensive and still does not increase the quality of the devices being manufactured. Also, sophisticated random sampling techniques are used that increase productivity slightly, but such statistical sampling techniques still allow a significant number of defective devices to pass through the test process undetected. Furthermore, since the existing processes sample and retest devices, if actual tester equipment failures are not identified immediately, then several lots of defective ICs can be "passed" before the equipment failure is identified. Nevertheless, the semiconductor industry has long justified the existing Lot Accept Test process with the questionable philosophy that a defective test system is more likely to fail a good lot than pass a bad one.
FIG. 1 is a diagram depicting a typical automated test system that is used for final testing of semiconductor ICs. Test system 1 includes three main components: an automated tester 2, a device-under-test (DUT) interface unit 4 (commonly referred to as a load board), and a device handler 8. Tester 2, which includes a digital processor and associated electronics, is software driven. The tester is physically and electrically connected to the load board 4. The operating surface of the load board is located proximate to the handler 8. Simplistically speaking, the handler places each device under test into an electrical socket located on the operating surface of the load board. The load board contains the electronic circuits that generate the test voltages and signals for the device connected to the socket. Tester 2, under the control of resident software routines, controls the operating environment of the tests (e.g., handler test temperature, soak time, etc.), provides digital instructions to, and receives test data from, the load board circuits and thus determines the performance or quality of each device being tested. The tester sends sorting instructions, via a data/command communications line 6, to the handler. Based on the results of the tests, the tester instructs the handler to convey each tested device to the appropriate output portion (e.g., "pass" or "fail" portion) of the sort/unload section 9 of the handler.
FIG. 2 illustrates the flow of an existing Lot Accept Test process used for final testing of semiconductor devices. At the onset (step 20), an operator determines whether the tester 2 (FIG. 1) has been calibrated and is otherwise available to begin the testing process. If the tester is not released, then the test process stops (step 30). Once the tester has been released for testing, the lot to be tested is loaded into the handler (step 40). After the devices are loaded, the operator initiates the actual test process (step 50). After testing of the lot is completed (step 60), the devices that "passed" should be ready for shipping (step 80) but are "shelved," while either all or a random sample of the devices that "passed" are retested (step 70). As discussed above, the results of the sampling and retesting process are used to verify that the test equipment was operating properly during the original tests. Following the retesting, passing devices are packed and shipped (step 80). However, as discussed above, there are numerous problems with the existing QA and final test processes.